1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a redundancy circuit of the semiconductor memory device which is capable of repairing in a package state the fail cells detected after burn-in test.
2. Description of the Related Art
As the semiconductor memory device becomes more and more highly integrated, the number of the memory cells and consequently the number of the fail cells within a chip are increase. Generally, the burn-in test is used to detect these fail cells. Accordingly, the semiconductor memory device should be provided with a redundancy circuit and a redundant memory cell array for repairing the fail cells detected after the burn-in test.
As described in FIG. 1, the operations of fabrication out, pre-laser sorting, laser-repair and sorting are sequentially performed in a wafer state. Thereafter, the burn-in test for removing the fail cells is performed after the package assembly and package sorting in package state.
The fail cell detected in the burn-in test is mainly caused by a single bit fail. The burn-in test is performed for detecting the fail memory cells or testing strength of the memory cells by providing an external power supply voltage or a higher voltage to each memory cell for long time so as to screen the fail cells. The fail cells screened during the burn-in test are discarded even though these have been processed through the test and assembly steps. This results in increasing the time and cost required in repairing the fail cells.
All semiconductor memory devices are therefore provided with the redundancy circuit and redundant memory cell array for repairing the fail cells with redundant cells. The redundancy operation is performed by decoding the address signal designating any fail, cell of the normal memory cell array and then selecting the redundant row or column connected to the redundant memory cell. Such an operation is performed by a redundancy decoder, and whether or not the normal decoder and redundancy decoder are enabled is determined by the output signal of the redundancy circuit for programming the fail addresses. When enabling the redundancy decoder, the redundancy operation is performed by laser-cutting the fuses in the redundancy circuit according to the addresses to be decoded.
FIG. 2 is a diagram illustrating a prior art redundancy circuit. When the fail cells are detected and the redundancy operation is performed, the enable fuses MF1 to MF4 are cut off, to enable the output of the address which is to be decoded. The fuses F1 to F16 are for transmitting the addresses to be decoded, and all the fuses except those connected to the addresses to be decoded are cut off during the redundancy operation so as to avoid the output of the addresses which are not to be decoded. The transmission gates G1 to G16 are turned on during the redundancy operation and are turned off, otherwise. The addresses RA0 to RA3, RB0 to RB3, RC0 to RC3 and RD0 to RD3 are respectively applied from the predecoders (not shown).
The signals AT, BT, CT find DT are respectively outputted from the transmission gates G1 to G16 receiving the addresses RA0 to RA3, RB0 to RB3, RC0 to RC3 and RD0 to TD3. The addresses RA0 to RA3 are inputted and the signal AT is outputted from the fuse corresponding to the fail address. The addresses RB0 to RB3 are inputted and the signal BT is outputted from the fuse corresponding to the fail address. The addresses RC0 to RC3 are inputted and the signal CT is outputted from the fuse corresponding to the fail address. And the addresses RD0 to RD3 are inputted and the signal DT is outputted from the fuse corresponding to the fail address.
The signal ABT is obtained by logic-operating the signals AT and BT through a NAND gate 8, and the signal CDT is obtained by logic-operating the signals CT and DT through a NAND gate 10. An output signal .phi. Ri (i=1,2,3,4) of a NOR gate 12 controls the redundancy decoder or normal decoder.
When no fail cell occurs in the normal memory cell array, the fuses of FIG. 2 are not cut off thus turning off the transmission gates G1 to G16. At this time, one input of each of the NAND gates 8 and 10 goes to a logic "low" state by the enable fuses MF3 and MF4. Thus, the NAND gates 8 and 10 respectively output the signals ABT and CDT of logic "high" state, and the NOR gate 12 outputs the output signal .phi. Ri (i=1,2,3,4) of logic "low" state. The output signal .phi. Ri of logic "low" state enables the normal decoder and disables the redundancy decoder.
When some fail cells occurs in the normal memory cell array, the enable fuses MF1 to MF4 are all cut off, thus enabling a redundancy operation. And the transmission gates G1 to G16 are all turned on, transmitting the received addresses. The fuses except those connected to the addresses to be decoded are all cut off, enabling only the address which is to be decoded (that is, the address designating a predetermined fail cell) to be outputted. For instance, in order to decode the addresses A0, B0, C0 and D0 and to repair the cells corresponding thereto, the fuses except F1, F5, F9 and F13 (in total, 16 fuses including enable fuses MF1 to MF4) should be cut off.
Thereby, the signals AT, BT, CT and DT become the logic "high" state, and the signals ABT and CDT go to the logic "low" state. The NOR gate 12 outputs the output signal .phi. Ri of logic "high" state, disabling the normal decoder and enabling the redundancy decoder. However, when decoding a predetermined address at the redundancy operation, the redundancy circuit of FIG. 2 should cut off all the fuses except those connected to the addresses to be decoded. This causes an inefficiency of cutting off 16 fuses in order to receive 4 address signals. In addition, if the fuses that should be cut off are not cut off, the repair operation may not be performed thus lowering the reliability of the redundancy circuit.
The conventional burn-in test has some problems of increasing time and cost required in repairing the fail cells and lowering the burn-in yield. Conventional redundancy circuits of various forms have been provided, however, repairing fail cells has not been properly performed for failures due to a single bit fail, even though a series of operations in the package state have been performed. In addition, there are too many fuses in the redundancy circuit to cut off the fuses effectively. And the disable of the redundancy operation caused by not properly cutting off the fuses results in lowering the reliability of the semiconductor memory device.